1. Technical Field
The present invention relates to electronic testing techniques, and more particularly relates to an improved method and system for electronic self-testing.
2. Description of Related Art
Improvements in manufacturing processes are enabling integrated circuit devices to offer more functionality as the size of individual transistors contained therein get smaller and smaller, thus allowing more transistors to be packaged within an integrated circuit device. As the trend of integrating more functions in a single high performance integrated circuit device (also called a chip) continues, testing of such devices is crucial to ensure a proper functioning device. One test technique is to connect a device under test to an external tester, which applies input stimuli, captures the resulting output, and compares this captured output to an expected output to determine if the device is functioning properly. Rather than using a tester to apply external patterns, an alternate test technique known as Logical built-in self-test (LBIST) uses an embedded pseudo-random pattern generator to generate input values to apply to a device's internal scan chain. A functional cycle (one or more clock pulses) is then run, and the device's response is captured in scannable latches. These captured values can then be scanned out and compressed using a multiple input signature register (MISR) to generate a signature that can be compared with a known good signature see if there were any faults.
LBIST can also be used to test the frequency characteristics of a chip. Data is scanned into the scan latches at the front end of the circuit-under-test. Then, after waiting a few cycles for the scan paths to stabilize, two functional clock cycles are issued back to back. The first functional clock cycle captures the scanned in data, which causes a signal transition to begin propagating through the circuits towards a capture latch's output. This transition occurs when the scanned in data is different from the data at the normal input to the circuit, thus causing a change in state at the output of the circuit and hence a signal transition. That transition is then captured during the second functional clock cycle by other capture latches. If the frequency is too fast, the second functional clock will be issued before the transition can propagate to the capture latch, and a fault will occur and be detected by LBIST. By increasing the frequency until a fault is produced, the highest operational frequency of the circuit can be found.
A chip will normally have various clocks and control methods to test and operate the chip. The master clock is the clock that drives the data input stage of a master-slave flip-flop latch, and the slave clock is the clock that drives the output stage of a master-slave flip-flop latch. The scan clocking scheme is used to scan data into and out of the scan latches.
As chips are getting larger and larger, it sometimes takes multiple cycles for data to get from one part of the chip to another. If a signal is going to take more than one cycle to get to its destination, it must be latched for each cycle. However, due to placement restrictions, timing and area concern, it is often desirable to use non-scan latches for this purpose. Then, during testing, the clocks to these latches are left running to propagate data through to the receiving scannable latch. However, this causes a problem when trying to characterize the frequency of the device during an AC test. Because the latches propagating the data are non-scan, there is no way to produce a transition that can be captured by the latches at the receiving end in one cycle since it takes multiple cycles for data to get from one part of the chip to another. This can be solved by issuing more functional cycles, but that makes diagnosing and isolating the fails much more difficult.
It would thus be desirable to provide an improved way for characterizing the AC operational speed of an electronic device.